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october 2002 1/18 p ? vnq600a(8960) quad channel high side solid state relay n dc short circuit current: 25a n cmos compatible inputs n proportional load current sense n undervoltage & overvoltage n shut-down n overvoltage clamp n thermal shut-down n current limitation n very low stand-by power dissipation n protection against: n loss of ground & loss of v cc n reverse battery protection (**) description the vnq600a(8960) is a quad hsd formed by assembling two vnd600 chips in the same so-28 package. the vnd600 is a monolithic device designed in | stmicroelectronics vipower m0-3 technology. the vnq600a(8960) is intended for driving any type of multiple loads with one side connected to ground. this device has four independent channels and four analog sense outputs which deliver currents proportional to the outputs currents. active current limitation combined with thermal shut-down and automatic restart protect the device against overload. device automatically turns off in case of ground pin disconnection. type r ds(on) (*) i lim v cc vnq600a(8960) 30m w 25a 36 v (*) per each channel at v cc =13v absolute maximum rating (**) see application schematic at page 9. symbol parameter value unit v cc supply voltage (continuous) 41 v -v cc reverse supply voltage (continuous) -0.3 v i out output current (continuous), for each channel 15 a i r reverse output current (continuous), for each channel -15 a i in input current +/- 10 ma v csense current sense maximum voltage -3 +15 v v i gnd ground current at t pins < 25 c (continuous) -200 ma v esd electrostatic discharge (human body model: r=1.5k w; c=100pf) - input - current sense - output - v cc 4000 2000 5000 5000 v v v v e max maximum switching energy (l=0.11mh; r l =0 w ; v bat =13.5v; t jstart =150oc; i l =40a) 126 mj p tot power dissipation (per island) at t lead =25c 6.25 w t j junction operating temperature internally limited c t stg storage temperature -55 to 150 c so-28 (double island) order codes package tube t&r so-28 vnq600a(8960) vnq600a(8960)tr
2/18 vnq600a(8960) block diagram logic undervoltage overvoltage overtemp. 1 overtemp. 2 i lim2 demag 2 k i out2 i lim1 demag 1 k i out1 input 1 input 2 gnd 1,2 v cc 1,2 output 1 current sense 1 output 2 current sense 2 driver 2 driver 1 logic undervoltage overvoltage overtemp. 3 overtemp. 4 i lim4 demag 4 k i out4 i lim3 demag 3 k i out3 input 3 input 4 gnd 3,4 v cc 3,4 output 3 current sense 3 output 4 current sense 4 driver 4 driver 3
3/18 vnq600a(8960) current and voltage conventions v cc 1,2 gnd 1,2 input2 input1 current v cc 1,2 v cc 3,4 gnd 3,4 input4 input3 v cc 3,4 sense 1 v cc 3,4 output 4 output 4 output 4 output 3 output 2 output 2 output 2 output 1 v cc 1,2 output 3 output 3 output 1 output 1 current sense 2 current sense 3 current sense 4 1 14 15 28 connection diagram (top view) i s3,4 i gnd1,2 output3 v cc3,4 gnd 1,2 input2 i out3 v cc3,4 v out4 output2 i out2 v out3 input1 i in1 cur. sense1 i sense1 output1 i out1 output4 i out4 v out2 v out1 i in2 i sense2 i sense3 i in4 i sense4 cur. sense2 cur. sense3 cur. sense4 input3 input4 v sense4 v in4 v sense3 v in3 v sense2 i in3 v in2 v sense1 v in1 i gnd3,4 gnd 3,4 i s1,2 v cc1,2 v cc1,2
4/18 vnq600a(8960) thermal data (per island) (*) when mounted on a standard single-sided fr-4 board with 0.5cm 2 of cu (at least 35 m m thick) connected to all v cc pins. horizontal mounting and no artificial air flow. electrical characteristics (8v 5/18 vnq600a(8960) current sense (9v < v cc < 16v) (see fig. 3) logic input note 1: v clamp and v ov are correlated. typical difference is 5v. note 2: current sense signal delay after positive input slope. note: sense pin doesnt have to be left floating. symbol parameter test conditions min typ max unit k 1 i out /i sense i out1,2 =0.35a; v sense =0.5v; t j = -40c...+150c 3300 4350 6000 dk 1 /k 1 current sense ratio drift i out1 or i out2 =0.5a; v sense =0.5v; other channels open; t j = -40c...150c -10 +10 % k 2 i out /i sense i out =2a; v sense =2.5v; t j =-40c t j = 25c...+150c 3900 4150 4850 4850 6000 5800 dk 2 /k 2 current sense ratio drift i out1 or i out2 =5a; v sense =4v; other channels open; t j =-40c...150c -6 +6 % k 3 i out /i sense i out =4a; v sense =4v; t j =-40c t j = 25c...+150c 4150 4400 4900 4900 6000 5750 dk 3 /k 3 current sense ratio drift i out1 or i out2 =15a; v sense =4v; other channels open; t j =-40c...150c -6 +6 % v sense1,2 max analog sense output voltage v cc =5.5v; i out1,2 =2a; r sense =10k w v cc >8v; i out1,2 =4a; r sense =10k w 2 4 v v v senseh analog sense output voltage in overtemperature condition v cc =13v; r sense =3.9k w 5v r vsenseh analog sense output impedance in overtemperature condition v cc =13v; t j >t tsd ; all channels open 400 w t dsense current sense delay response to 90% i sense (see note 2) 500 m s symbol parameter test conditions min typ max unit v il low level input voltage 1.25 v v ih high level input voltage 3.25 v v i(hyst) input hysteresis voltage 0.5 v i il low level input current v in =1.25v 20 65 m a i ih high level input current v in =3.25v 75 110 m a v icl input clamp voltage i in =1ma i in = -1ma 66.8 -0.7 8v v 2
6/18 vnq600a(8960) conditions input output sense normal operation l h l h 0 nominal overtemperature l h l l 0 v senseh undervoltage l h l l 0 0 overvoltage l h l l 0 0 short circuit to gnd l h h l l l 0 (t j t tsd ) v senseh short circuit to v cc l h h h 0 < nominal negative output voltage clamp ll 0 truth table (per channel)
7/18 vnq600a(8960) electrical transient requirements figure 1: switching characteristics (resistive load r l =2.6 w ) iso t/r 7637/1 test pulse test levels i test levels ii test levels iii test levels iv test levels delays and impedance 1 -25v -50v -75v -100v 2ms, 10 w 2 +25v +50v +75v +100v 0.2ms, 10 w 3a -25v -50v -100v -150v 0.1 m s, 50 w 3b +25v +50v +75v +100v 0.1 m s, 50 w 4 -4v -5v -6v -7v 10ms, 0.01 w 5 +26.5v +46.5v +66.5v +86.5v 400ms, 2 w iso t/r 7637/1 test pulse test levels result i test levels result ii test levels result iii test levels result iv 1 cc cc 2 cc cc 3a cc cc 3b cc cc 4 cc cc 5 ce ee class contents c all functions of the device are performed as designed after exposure to disturbance. e one or more functions of the device is not performed as designed after exposure and cannot be returned to proper operation without replacing the device. 1 v out dv out /dt (on) t r 80% 10% t f dv out /dt (off) i sense t t 90% t d(off) input t 90% t d(on) t dsense
8/18 vnq600a(8960) sense n input n normal operation undervoltage v cc v usd v usdhyst input n overvoltage v cc sense n input n sense n figure 2: waveforms (per each chip) load current n load current n load current n overtemperature input n sense n t tsd t r t j load current n v ov v cc > v ov v cc < v ov short to ground input n load current n sense n load voltage n input n load voltage n sense n load current n 9/18 vnq600a(8960) gnd protection network against reverse battery solution 1: resistor in the ground line (r gnd only). this can be used with any type of load. the following is an indication on how to dimension the r gnd resistor. 1) r gnd 600mv / 2(i s(on)max ). 2) r gnd 3 (- v cc ) / (-i gnd ) where -i gnd is the dc reverse ground pin current and can be found in the absolute maximum rating section of the devices datasheet. power dissipation in r gnd (when v cc <0: during reverse battery situations) is: p d = (-v cc ) 2 /r gnd this resistor can be shared amongst several different hsd. please note that the value of this resistor should be calculated with formula (1) where i s(on)max becomes the sum of the maximum on-state currents of the different devices. please note that if the microprocessor ground is not common with the device ground then the r gnd will produce a shift (i s(on)max * r gnd ) in the input thresholds and the status output values. this shift will vary depending on how many devices are on in the case of several high side drivers sharing the same r gnd . if the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then the st suggests to utilize solution 2 (see below). solution 2: a diode (d gnd ) in the ground line. a resistor (r gnd =1k w) should be inserted in parallel to d gnd if the device will be driving an inductive load. this small signal diode can be safely shared amongst several different hsd. also in this case, the presence of the ground network will produce a shift ( j 600mv) in the input threshold and the status output values if the microprocessor ground is not common with the device ground. this shift will not vary if more than one hsd shares the same diode/resistor network. load dump protection d ld is necessary (voltage transient suppressor) if the load dump peak voltage exceeds v cc max dc rating. the same applies if the device will be subject to transients on the v cc line that are greater than the ones shown in the iso t/r 7637/1 table. 1 application schematic v cc1,2 output2 c. sense 1 d ld +5v r prot output1 r sense1,2,3,4 input1 c. sense 2 input2 m c r prot r prot r prot input3 input4 c. sense 3 c. sense 4 d gnd r gnd v gnd gnd1,2 gnd3,4 output3 r prot r prot r prot r prot v cc3,4 output4 note: channels 3 & 4 have the same internal circuit as channel 1 & 2.
10/18 vnq600a(8960) m c i/os protection: if a ground protection network is used and negative transients are present on the v cc line, the control pins will be pulled negative. st suggests to insert a resistor (r prot ) in line to prevent the m c i/os pins to latch-up. the value of these resistors is a compromise between the leakage current of m c and the current required by the hsd i/os (input levels compatibility) with the latch-up limit of m c i/os. -v ccpeak /i latchup r prot (v oh m c -v ih -v gnd ) / i ihmax calculation example: for v ccpeak = - 100v and i latchup 3 20ma; v oh m c 3 4.5v 5k w r prot 6k w . recommended r prot value is 5k w. 0246810121416 3000 3500 4000 4500 5000 5500 6000 6500 min.tj=-40c max.tj=-40c min.tj=25...150c max.tj=25...150c typical value figure 3: i out /i sense versus i out i out /i sense i out (a)
11/18 vnq600a(8960) high level input current input clamp voltage off state output current -50 -25 0 25 50 75 100 125 150 175 tc (c) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 iih (ua) vin=3.25v -50 -25 0 25 50 75 100 125 150 175 tc (c) 6 6.2 6.4 6.6 6.8 7 7.2 7.4 7.6 7.8 8 vicl (v) iin=1ma input high level -50 -25 0 25 50 75 100 125 150 175 tc (c) 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 vih (v) input hysteresis voltage input low level -50 -25 0 25 50 75 100 125 150 175 tc (c) 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 vil (v) -50 -25 0 25 50 75 100 125 150 175 tc (c) 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 vhyst (v) -50 -25 0 25 50 75 100 125 150 175 tc (c) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 il(off1) (ua) off state vcc=36v vin=vout=0v
12/18 vnq600a(8960) overvoltage shutdown turn-on voltage slope turn-off voltage slope i lim vs t case -50 -25 0 25 50 75 100 125 150 175 tc (c) 30 32 34 36 38 40 42 44 46 48 50 vov (v) -50 -25 0 25 50 75 100 125 150 175 tc (oc) 250 300 350 400 450 500 550 600 650 700 750 dvout/dt(on) (v/ms) vcc=13v rl=2.6ohm -50 -25 0 25 50 75 100 125 150 175 tc (oc) 0 50 100 150 200 250 300 350 400 450 500 dvout/dt(off) (v/ms) vcc=13v rl=2.6ohm on state resistance vs t case on state resistance vs v cc -50 -25 0 25 50 75 100 125 150 175 tc (c) 0 10 20 30 40 50 60 70 80 ilim (a) vcc=13v -75 -50 -25 0 25 50 75 100 125 150 175 tc (c) 0 10 20 30 40 50 60 70 80 90 100 ron (mohm) iout=5a 8v 13/18 vnq600a(8960) maximum turn off current versus load inductance a = single pulse at t jstart =150oc b= repetitive pulse at t jstart =100oc c= repetitive pulse at t jstart =125oc conditions: v cc =13.5v values are generated with r l =0 w in case of repetitive pulses, t jstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves b and c. v in , i l t demagnetization demagnetization demagnetization 1 10 100 0.001 0.01 0.1 1 10 100 l(mh) i lmax (a) a b c
14/18 vnq600a(8960) so-28 double island pc board thermal calculation according to the pcb heatsink area r tha = thermal resistance junction to ambient with one chip on r thb = thermal resistance junction to ambient with both chips on and p dchip1 =p dchip2 r thc = mutual thermal resistance r thj-amb vs pcb copper area in open box free air condition chip 1 chip 2 t jchip1 t jchip2 note on off r tha x p dchip1 + t amb r thc x p dchip1 + t amb off on r thc x p dchip2 + t amb r tha x p dchip2 + t amb on on r thb x (p dchip1 + p dchip2 ) + t amb r thb x (p dchip1 + p dchip2 ) + t amb p dchip1 =p dchip2 on on (r tha x p dchip1 ) + r thc x p dchip2 + t amb (r tha x p dchip2 ) + r thc x p dchip1 + t amb p dchip1 1 p dchip2 so-28 double island thermal data layout condition of r th and z th measurements (pcb fr4 area= 58mm x 58mm, pcb thickness=2mm, cu thickness=35 m m, copper areas: 0.5cm 2 , 3cm 2 , 6cm 2 ). 10 20 30 40 50 60 70 01234567 pcb cu heatsink area (cm ^2)/island rthj_am b (c/w) r tha r thb r thc
15/18 vnq600a(8960) thermal fitting model of a four channels hsd in so-28 pulse calculation formula thermal parameter area/island (cm 2 )0.56 r1=r7=r13=r15 (c/w) 0.05 r2=r8=r14=r16 (c/w) 0.3 r3=r9 (c/w) 3.4 r4=r10 (c/w) 11 r5=r11 (c/w) 15 r6=r12 (c/w) 30 13 c1=c7=c13=c15 (w.s/c) 0.001 c2=c8=c14=c16 (w.s/c) 5.00e-03 c3=c9 (w.s/c) 1.00e-02 c4=c10 (w.s/c) 0.2 c5=c11 (w.s/c) 1.5 c6=c12 (w.s/c) 5 8 r17=r18 (c/w) 150 z th d r th d z thtp 1 d C () + = where d t p t = so-28 thermal impedance junction ambient single pulse 0.01 0.1 1 10 100 0.0001 0.001 0.01 0.1 1 10 100 1000 time(s) zth(c/w) 6 cm ^2/is land 3 cm ^2/island 0,5 cm ^2/island one channel on two channels on on same chip pd1 c1 r4 c3 c4 r3 r1 r6 r5 r2 c5 c6 c2 pd2 r14 c13 c1 4 r13 tj_1 tj_2 t_amb pd3 c7 r10 c9 c10 r9 r7 r12 r11 r8 c1 1 c1 2 c8 pd4 r16 c15 c16 r15 tj_3 tj_4 r17 r18
16/18 vnq600a(8960) dim. mm. inch min. typ max. min. typ. max. a2.650.104 a1 0.10 0.30 0.004 0.012 b 0.35 0.49 0.013 0.019 b1 0.23 0.32 0.009 0.012 c 0.50 0.020 c1 45 (typ.) d 17.7 18.1 0.697 0.713 e 10.00 10.65 0.393 0.419 e 1.27 0.050 e3 16.51 0.650 f 7.40 7.60 0.291 0.299 l 0.40 1.27 0.016 0.050 s 8 (max.) 2 so-28 mechanical data
17/18 vnq600a(8960) so-28 tube shipment (no suffix) all dimensions are in mm. base q.ty 28 bulk q.ty 700 tube length ( 0.5) 532 a 3.5 b 13.8 c ( 0.1) 0.6 tape and reel shipment (suffix tr) base q.ty 1000 bulk q.ty 1000 a (max) 330 b (min) 1.5 c ( 0.2) 13 f 20.2 g (+ 2 / -0) 16.4 n (min) 60 t (max) 22.4 tape dimensions according to electronic industries association (eia) standard 481 rev. a, feb 1986 all dimensions are in mm. tape width w 16 tape hole spacing p0 ( 0.1) 4 component spacing p 12 hole diameter d ( 0.1/-0) 1.5 hole diameter d1 (min) 1.5 hole position f ( 0.05) 7.5 compartment depth k (max) 6.5 hole spacing p1 ( 0.1) 2 top cover tape end start no components no components components 500mm min 500mm min empty components pockets saled with cover tape. user direction of feed a c b reel dimensions
18/18 vnq600a(8960) information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this p ublication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectron ics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicr oelectronics. the st logo is a trademark of stmicroelectronics ? 2002 stmicroelectronics - printed in italy- all rights reserved. stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com

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